1. Field of the Invention
The present invention relates to diodes in silicon-on-insulator (SOI) CMOS process, and more particularly to ESD protection circuits with the diodes in silicon-on-insulatorCMOS process.
2. Description of the Prior Art
Silicon-on-insulator technology is a prime contender for low voltage, high speed applications because of its advantages over bulk-Si technology in reduced process complexity, latch-up immunity and smaller junction capacitance. However, electrostatic discharge (ESD) is a major reliability concern for SOI technology.
The protection level provided by an ESD protection device is determined by the amount of current that it can sink. The device failure is initiated by thermal runaway and followed by catastrophic damage during an ESD pulse. In SOI devices, the presence of the buried oxide layer having a thermal conductivity {fraction (1/100)}th of Si causes increased device's heating, which in turn accelerates thermal runaway.
FIG. 1 depicts a cross-sectional view of a prior SOI diode, called as Lubistor diode, published in the article of the Proc. Of EOS/ESD Symp., 1996, pp. 291-301. If the silicon layer above the buried oxide layer 100 is doped N type dopant, the junction of the SOI diode is P+ 102/N well 101. The two terminals of this junction diode are V1 connected to P+ 102 and V2 connected to N well 101. If V1 is positive relative to V2, the SOI diode is under forward biased. However, if V1 is negative relative to V2, the diode is under reverse biased. If the P+ 102/N well 101 (or N+/P well) junction area in which the power is generated during an ESD event is smaller, then it will increase power density and heat. The heat is generated in a localized region at the P-N junction and the dominant component of the heat at the junction is Joule heat. Second breakdown is assumed to occur when the maximum temperature in the SOI diode reaches the intrinsic temperature (Tintrinsic). In order to get better ESD protection level, one should reduce the power density and Joule heat.
Accordingly, it is a desirability to provide a diode with lower power density in silicon-on-insulator CMOS process for ESD protection.